The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 08, 2002

Filed:

Mar. 30, 2000
Applicant:
Inventors:

Jay P. John, Chandler, AZ (US);

James A. Kirchgessner, Tempe, AZ (US);

Ik-Sung Lim, Gilbert, AZ (US);

Michael H. Kaneshiro, Phoenix, AZ (US);

Vida Ilderem Burger, Phoenix, AZ (US);

Phillip W. Dahl, Gilbert, AZ (US);

David L. Stolfa, Moab, UT (US);

Richard W. Mauntel, Phoenix, AZ (US);

John W. Steele, Chandler, AZ (US);

Assignee:

Motorola, Inc., Schaumburg, IL (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/1331 ;
U.S. Cl.
CPC ...
H01L 2/1331 ;
Abstract

A method of manufacturing a heterojunction BiCMOS IC. ( ) includes forming a gate electrode ( ), forming a protective layer ( ) over the gate electrode, forming a semiconductor layer ( ) over the protective layer, depositing an electrically insulative layer ( ) over the semiconductor layer, using a mask layer ( ) to define a doped region ( ) in the semiconductor layer and to define a hole ( ) in the electrically insulative layer, forming an electrically conductive layer ( ) over the electrically insulative layer, using another mask layer ( ) to define an emitter region ( ) in the electrically conductive layer and to define an intrinsic base region ( ) and a portion of an extrinsic base region ( ) in the electrically conductive layer, and using yet another mask layer ( ) to define another portion of the extrinsic base region in the electrically conductive layer.


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