The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 08, 2002
Filed:
Aug. 26, 1999
Peter A. Gruber, Mohegan Lake, NY (US);
Frederic Maurer, Valhalla, NY (US);
Lubomyr Taras Romankiw, Briarcliff Manor, NY (US);
International Business Machines Corp., Armonk, NY (US);
Abstract
An apparatus and a method for filling high aspect ratio holes in electronic substrates that can be advantageously used for filling holes having aspect ratios larger than 5:1 are disclosed. In the apparatus, a filler plate and a vacuum plate are used in conjunction with a connection means such that a gap is formed between the two plates to accommodate an electronic substrate equipped with high aspect ratio via holes. The filler plate is equipped with an injection slot while the vacuum plate is equipped with a vacuum slot such that when a substrate is sandwiched therein, via holes can be evacuated of air and injected with a liquid simultaneously from a bottom side and a top side of the substrate. The present invention novel apparatus and method allows the filling of via holes that have small diameters, i.e., as small as 10 &mgr;m, and high aspect ratios, i.e., at least 5:1 to be filled with an electrically conductive material such as a solder or a conductive polymer such that vias or interconnects can be formed in electronic substrates. The present invention apparatus and method can be advantageously used in fabricating substrates for display panels by forming conductive vias and interconnects for placing a voltage potential on pixel display elements formed on the display panels.