Apparatus for testing semiconductor device

Abstract

A multi-way interleave-type semiconductor device testing apparatus is provided, which is capable of testing an IC under test in either case that the latency (the number of delay cycles) N of the IC under test is an odd number or an even number. In each of plural test circuit units ( - and - ) is provided a clock control circuit ( ) comprising an adder for adding up the test period Tr of the IC tester and a clock setting value Tc, and a selector ( ) for selecting the output from the adder or the clock setting value Tc to output the selected one. The latency is set in a delay setting register ( ) which supplies to the selector a binary number “0” when the latency is an even number and a binary number “1” when the latency is an odd number. The selector outputs the clock setting value in case of “0” and outputs the sum of the test period and the clock setting value in case of “1”, so that a clock generator ( ) outputs the period signal of the test circuit unit at a timing corresponding to the input signal. In a pattern delay circuit ( ) is set a delay time obtained by multiplication of the period of the period signal by a decimal number supplied from the delay setting register, thereby to delay an expected value signal EXP to supply it to a logical comparator ( ).