The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 24, 2002

Filed:

Mar. 15, 2000
Applicant:
Inventors:

Akira Asai, Osaka, JP;

Teruhito Oonishi, Osaka, JP;

Takeshi Takagi, Kyoto, JP;

Tohru Saitoh, Osaka, JP;

Yoshihiro Hara, Osaka, JP;

Koichiro Yuki, Osaka, JP;

Katsuya Nozawa, Osaka, JP;

Yoshihiko Kanzawa, Osaka, JP;

Koji Katayama, Nara, JP;

Yo Ichikawa, Aichi, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/18249 ;
U.S. Cl.
CPC ...
H01L 2/18249 ;
Abstract

In the method for fabricating a semiconductor device of the present invention, a collector layer of a first conductivity type is formed in a region of a semiconductor substrate sandwiched by device isolation. A collector opening is formed through a first insulating layer deposited on the semiconductor substrate so that the range of the collector opening covers the collector layer and part of the device isolation. A semiconductor layer of a second conductivity type as an external base is formed on a portion of the semiconductor substrate located inside the collector opening, while junction leak prevention layers of the same conductivity type as the external base are formed in the semiconductor substrate. Thus, the active region is narrower than the collector opening reducing the transistor area, while minimizing junction leak.


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