The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 17, 2002
Filed:
Apr. 16, 2001
Pi-Cheng Chen, Hsin-Chu, TW;
Wen-Hao Chen, Chiao-Tou, TW;
Ming-Chyuan Chen, Hsinchu, TW;
Hsien-Te Chen, Hsin-Chu, TW;
Taiwan Semiconductor Manufacturing Company, Hsin-Chu, TW;
Abstract
In the present invention a method is described to produce a whole chip timing verification that includes the effects of voltage variation on delay. This is done by creating a netlist, defining cell input and output (I/O) delay paths, and calculating the difference timing caused by differences in power supply voltage. The incremental I/O path delay is calculated by adding delay changes caused by all power pins. Whole chip timings are generated without consideration to voltage drops and then modified using the incremental path delay. The modified whole chip timing data file is used with traditional timing verification tools to perform a whole chip cell level timing verification.