Computer system having a bus interface unit for prefetching data from system memory

Abstract

A computer system, a bus interface unit, and a method for prefetching data from system memory to a central processing unit (CPU). The system includes a dynamic random access memory (DRAM) connected to a high speed bus, a CPU and a bus interface unit that allows the CPU to communicate with the high speed bus. The bus interface unit contains logic circuitry, so that when the CPU generates a read memory access request for information associated with a first address, the interface unit generates a request a packet for the information and prefetch information associated with a prefetch address. The bus interface unit creates the request packet by increasing the number of addresses originally requested by the CPU. The interface then sends the request packet to the system memory device, which retrieves and returns the requested data. The interface may include a pair of buffers which store both the information requested by the CPU and speculative or prefetch information. When the CPU generates a subsequent request, the interface compares the addresses requested with addresses in the prefetch buffer. If the buffer contains the addresses, the data is sent to the processor. The prefetch buffer is directly addressable so that any line within the buffer can be retrieved.