The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 17, 2002

Filed:

Dec. 14, 2000
Applicant:
Inventors:

Kwon Hong, Kyoungki-do, KR;

Heung-Sik Kwak, Kyoungki-do, KR;

Chung-Tae Kim, Kyoungki-do, KR;

Hyung-Bok Choi, Kyoungki-do, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/18242 ; C25D 5/02 ;
U.S. Cl.
CPC ...
H01L 2/18242 ; C25D 5/02 ;
Abstract

A method for manufacturing a semiconductor device can form a thick lower electrode made of Pt. The method begins with the preparation of an active matrix provided with at least one transistor, a plurality of conductive plugs electrically connected to the transistors and an insulating layer formed around the conductive plugs. Thereafter, a seed layer is formed on top of the active matrix and a dummy oxide layer is formed on top of the seed layer. Then, the dummy oxide layer is patterned into a predetermined configuration, thereby exposing portions of the seed layer which are located on top of the conductive plugs. The exposed portions are filled with a conductive material to a predetermined thickness. The dummy oxide layer and portions of the seed layer which are not covered with the conductive material are removed, thereby obtaining lower electrodes. A capacitor dielectric layer is on the lower electrodes. Finally, an upper electrode layer is formed on the capacitor dielectric layer.


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