The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 10, 2002

Filed:

Aug. 07, 2001
Applicant:
Inventors:

Erh-Kun Lai, Tai-Chung Hsien, TW;

Hsin-Huei Chen, Miao-Li Hsien, TW;

Shou-Wei Huang, Chi-Lung, TW;

Ying-Tso Chen, Kao-Hsiung Hsien, TW;

Chien-Hung Liu, Taipei, TW;

Shyi-Shuh Pan, Kao-Hsiung, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/18238 ;
U.S. Cl.
CPC ...
H01L 2/18238 ;
Abstract

A method of forming an embedded memory integrating nitride read only memory starts by forming an ONO layer and a protective cap layer on a surface of a semiconductor substrate defined with a memory area and a periphery area. The periphery area has a first, a second and a third device area. An etching and a first ion implantation process form each bit line in the memory area. A spacer is then formed at either side of the protective cap layer and the ONO layer in the memory area, and the protective cap layer and the ONO layer are removed in the first device area. The threshold voltage for the first device area is adjusted and a first thermal oxidation process forms a buried drain oxide layer atop each bit line and a first gate oxide layer on the surface of the first device area, respectively. The protective cap layer and the ONO layer are removed from the second device area and the third device area, and a second gate oxide layer is formed in the second device area and the third device area. Finally, the protective cap layer in the memory area and the second gate oxide layer in the third device area are removed, and a third gate oxide layer is formed in the third device area.


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