Master-slave flip-flop circuit with embedded hold function and method for holding data in a master-slave flip-flop circuit

Abstract

A master-slave flip-flop circuit ( ′) includes a master latch circuit ( ) and slave latch circuit ( ). A hold control component ( ) included in the master latch circuit ( ) is interposed between a master latch node (ML) and a slave input node (SI). The hold control component blocks the transfer of data from the master latch node (ML) to the slave input node (SI) in response to a hold input. In the preferred form of the invention of the hold control component ( ) comprises a tri-state inverter having an input connected to the master latch node (ML) and an output connected to the slave input node (SI). The hold input, comprising a high level hold signal and its complementary or inverted signal, disables the tri-state inverter and thus prevent data from being transferred from the master latch node (ML) to the slave input node (SI). When the hold input is removed, that is, when the hold signal is at a low logical level and complementary signal is at a high logical level, the master-slave flip-flop circuit ( ′) operates in the normal fashion, receiving and latching new data in each clock cycle and applying that new data to the circuit output.