Method of generating an optimal clock buffer set for minimizing clock skew in balanced clock trees

Abstract

The present invention has application to final balancing of an initial balanced clock tree. In one aspect of the invention, a minimum set of clock buffer delays is generated to reduce clock skew to within a selected skew limit for each level of a balanced clock tree. In one embodiment, the difference between the optimum delay and the clock buffer delay selected from the minimum set of clock buffer delays for each clock buffer in the balanced clock tree is less than or equal to the selected skew limit. In one such embodiment, a method of balancing a clock tree includes the steps of receiving as input a minimum buffer delay, a maximum level skew limit, and a selected skew limit; generating a minimum set of clock buffer delays for replacing at least one clock buffer in the balanced clock tree with a clock buffer delay selected from the minimum set of clock buffer delays such that the difference between the optimum delay and the clock buffer delay is less than or equal to the selected skew limit; and generating as output the minimum set of clock buffer delays.