Pre-decode conditional command generation for reduced sdram cycle latency

Abstract

A method and apparatus for reducing the latency of a cycle initiated by a bus-mastering agent to a memory array is described. The method and corresponding apparatus involves partially decoding a current memory cycle to generate intermediate signals and providing one or more “safe” indicator signals indicating the status of a previous memory cycle. A circuit receives the intermediate signals and the one or more safe indicator signals, and determines whether it is safe to issue a chip select to the memory array, notwithstanding the fact that the command to be issued to the memory array is not yet known. If the cycle is a page-hit, then no further commands or chip select signals are required for the balance of the memory cycle. If the cycle is a row-miss or page-miss, further chip select assertions are required and the responsibility to assert the chip select signal is transferred from the device to a finite state machine.