The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 27, 2002

Filed:

Dec. 03, 1999
Applicant:
Inventors:

Taylor Efland, Richardson, TX (US);

Chin-Yu Tsai, Plano, TX (US);

Sameer Pendharkar, Plano, TX (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/976 ; H01L 2/994 ; H01L 3/1062 ; H01L 3/1113 ; H01L 3/1119 ;
U.S. Cl.
CPC ...
H01L 2/976 ; H01L 2/994 ; H01L 3/1062 ; H01L 3/1113 ; H01L 3/1119 ;
Abstract

An embodiment of the instant invention is a transistor formed on a semiconductor substrate of a first conductivity type and having an upper surface, the transistor comprising: a well region (well of FIG. ) formed in the semiconductor substrate (layer of FIG. ), the well region of a second conductivity type opposite that of the first conductivity type; a source region (source region of FIG. ) formed in the well region in the semiconductor substrate, the source region of the second conductivity type; a drain region (drain of FIG. ) formed in the semiconductor substrate and spaced away from the source region by a channel region (given by length L +L ), the drain region of the second conductivity type; a conductive gate electrode (layer of FIG. ) disposed over the semiconductor substrate and over the channel region; a gate insulating layer (layer of FIG. ) disposed between the conductive gate electrode and the semiconductor substrate and having a length, the gate insulating layer comprising: a first portion of the gate insulating layer which has a first length (L ) and a first thickness; a second portion of the gate insulating layer which has a second length (L ) and a second thickness which is substantially thicker than the first thickness, the sum of the first length and the second length equalling the length of the gate insulating layer; and wherein the first portion of the gate insulating layer being situated proximate to the source region and spaced away from the drain region by the second portion of the gate insulating layer; and wherein the well region having a dopant concentration less than that of the source region and the drain region, the well region extends at least from source region towards the drain region so as to completely underlie the first portion of the gate insulating layer and to underlie at least the second portion of the gate insulating layer.


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