The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 27, 2002

Filed:

Oct. 16, 2000
Applicant:
Inventor:

Jing-Horng Gau, Hsinchu Hsien, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/18242 ;
U.S. Cl.
CPC ...
H01L 2/18242 ;
Abstract

A self-aligned bit-line contact opening and node contact opening fabrication process having the following features: Etching of the periphery MOS spacer is performed before ion implantation of the periphery MOS source/drain region, using the same photoresist layer as a mask. A self-aligned bit-line (node) contact opening and a periphery gate contact opening, above the periphery MOS gate, are formed simultaneously. The etching of the memory cell MOS spacer is performed after the self-aligned bit-line (node) contact opening has been formed. At the same time, the cap layer above the periphery MOS gate, exposed by the periphery gate contact opening, is etched through.


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