Wordline stress mode arrangement a storage cell initialization scheme test time reduction burn-in elimination

Abstract

An integrated circuit memory device includes a wordline stress mode arrangement and a storage cell initialization arrangement with the array of storage cells. In the wordline stress mode arrangement, a plurality of wordlines are run across the array. Each wordline is connected with the gates of transfer transistors of a different row of the storage cells. A decoder, responsive to a control signal, simultaneously applies a supply voltage to the wordlines. The supply voltage may be provided by a selectable magnitude external source. In the cell initialization arrangement, a plurality of complementary pairs of bitlines are run across the array. Each complementary pair of the bitlines interconnects with the storage cells in a separate column of the array. A precharge circuit is arranged for precharging the bitlines to a precharge voltage. a precharge disabling circuit, responsive to the control signal, disables the precharge circuit from applying the precharge voltage and supplies an alterntive voltage to the pairs of bitlines. A separate amplifier is connected with each separate pair of complementary bitlines. A control circuit, responsive to the control signal, disables operation of the amplifiers when the alternative voltage is supplied to the pairs of bitlines. Considerable testing time can be saved. Burn in stress testing can be eliminated.