Fabrication method and structure of a flash memory

Abstract

A fabrication method and a structure of a flash memory. Several first shallow trench isolations and second shallow trench isolations are formed in a memory circuit region and a peripheral circuit region of a substrate, respectively. The first shallow trench isolations are shallower than the second shallow trench isolations. Several gates are formed along a direction perpendicular to the substrate in the memory circuit region. A self-aligned source region process is performed to remove the isolation layer within every other first shallow trench isolations between the gates. A common source region and a column of separate drain regions are thus alternatively formed between the gates. The drain regions in the same column are isolated by the first shallow trench isolations.