The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 20, 2002
Filed:
Mar. 16, 2001
Andres Bryant, Essex Junction, VT (US);
Jerome B. Lasky, Essex Junction, VT (US);
Edward J. Nowak, Essex Junction, VT (US);
Jed H. Rankin, S. Burlington, VT (US);
Minh H. Tong, Fuquay-Varina, NC (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A semiconductor device having an SOI FET comprising a silicon body on an insulating layer on a conductive substrate. A gate dielectric and a gate are provided on a surface of the silicon body, and a source and a drain are provided on two sides of the gate. A buried body contact to the substrate conductor is provided below a third side of the gate. The buried body contact does not extend to the top surface of the silicon body. The body contact is separated from the gate by a second dielectric having a thickness typically greater than that of the gate dielectric. The body contact is a plug of conductive material, and the second dielectric coats the body contact under the gate. The FET can be used in an SRAM circuit or other type of circuit having a silicon-on-insulator (SOI) construction.