The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 13, 2002
Filed:
Apr. 20, 1998
Applicant:
Inventors:
Masamichi Kawarabayashi, Tokyo, JP;
Takuo Nakaki, Kanagawa, JP;
Assignee:
NEC Corporation, Tokyo, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/750 ; G06F 9/45 ;
U.S. Cl.
CPC ...
G06F 1/750 ; G06F 9/45 ;
Abstract
A method designs a logic circuit having a flip-flop which performs an on and off operation in response to a timing clock and a feedback loop. With such a structure, a logic circuit portion which operates in accordance with an enable signal automatically is extracted. Further, the logic circuit portion is formed by the use of a gated clock obtained by gating the timing clock via the enable signal. Thereby, the number of on and off operations of the flip-flop in response to the timing clock can be largely reduced.