The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 13, 2002

Filed:

Jun. 10, 1999
Applicant:
Inventor:

Morris E. Jones, Jr., Saratoga, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/5167 ; G06F 1/300 ;
U.S. Cl.
CPC ...
G06F 1/5167 ; G06F 1/300 ;
Abstract

A memory architecture for a video graphics controller includes a dynamic random access memory (DRAM), a static random access memory (SRAM) and a bus. The DRAM includes a data port, an address decoder that can receive an address to select a memory location in the DRAM and a command instruction bus that can receive instructions for data transfer. The SRAM includes a first data port to transfer data with the DRAM, a second data port to transfer data with other than the DRAM, a first address decoder that can receive an address to select a memory location in the SRAM for data transfer with the DRAM, a first read/write input that can receive a signal for data transfer with the DRAM, a second address decoder that can receive an address to select a memory location in a page of the SRAM to transfer data with other than the DRAM and a second read/write input that can receive a signal for data transfer from other than the DRAM. The bus is coupled between the data port of the DRAM and the first data port of the SRAM for data transfer between the DRAM and the SRAM.


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