The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 13, 2002

Filed:

Apr. 06, 1995
Applicant:
Inventors:

Marius Orlowski, Austin, TX (US);

Kuo-Tung Chang, Austin, TX (US);

Keith E. Witek, Austin, TX (US);

Jon Fitch, Austin, TX (US);

Assignee:

Motorola, Inc., Schaumburg, IL (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/9788 ;
U.S. Cl.
CPC ...
H01L 2/9788 ;
Abstract

A split-gate EEPROM transistor includes a channel region ( ) formed in a vertically disposed semiconductor body ( ) and residing intermediate to a drain region ( ) and a source region ( ). A select gate electrode ( ) is horizontally disposed on a semiconductor substrate ( ). A floating gate electrode ( ) resides adjacent to the channel region ( ) and overlies the select gate electrode ( ). A control gate electrode ( ) resides adjacent to the control gate electrode ( ) and also overlies the select gate electrode ( ). In operation, the select gate electrode ( ) regulates the flow of electrical charge from the source region ( ) into the channel region ( ), and provides a field plate electrical isolation for adjacent memory cells in an EEPROM array.


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