The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 06, 2002

Filed:

Sep. 09, 1996
Applicant:
Inventors:

Tah-Kang Joseph Ting, Hsinchu, TW;

Gyh-Bin Wang, Chung-Li, TW;

Chien-Te Wu, Hsinchu, TW;

Assignee:

Etron Technology, Inc., Hsin-chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/037 ;
U.S. Cl.
CPC ...
H03K 3/037 ;
Abstract

An improved input buffer circuit of the type having a chain of FET inverter circuits has an FET connected in a feedback loop that functions like a Schmidt trigger and counteracts a hysteresis effect that causes variations in the delay of the inverter circuits and compensation for process variation. An FET is connected to conduct in its source-drain circuit between one of the power supply terminals and the interconnection node of two of the inverters in the chain. The gate of FET is connected to receive a signal from the output of one of the inverters. The hysteresis effect is characterized by different rising and falling paths at one knee of the transfer curve that describes the switching operation. The channel type of the FET and the polarity of the power supply terminal are selected to provide feedback during the transition where the knee occurs.


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