Test structure and methodology for characterizing ion implantation in an integrated circuit fabrication process

Abstract

A test structure for characterizing ion implantation procedures used in integrated circuit fabrication processes and a method for using the test structure are described. The test structure includes a first dielectric layer, a patterned polysilicon layer, and a second dielectric layer arranged in order upon a substrate. Ion implantation of the second dielectric layer may be performed according to a procedure used in the fabrication of integrated circuits. The ion-implanted regions of the second dielectric layer may be preferentially removed relative to non-ion-implanted regions of the second dielectric layer. A metal silicide may then be selectively formed upon portions of the patterned polysilicon not covered by non-removed regions of the second dielectric layer. Electrical testing and/or optical inspection may be used to identify defects introduced into the test structure during ion implantation.