Architecture for field programmable gate array

Abstract

A field programmable gate array includes a programmable interconnect structure and plurality of logic cells. The logic cells each include a number of combinatorial logic circuits, which have direct interconnections with the programmable interconnect structure, and a plurality of sequential logic element, such as D type flip-flops that acts as registers. The combinatorial logic circuits may be directly connected to the programmable interconnect structure as well as connected to the input terminals of the sequential logic elements. Consequently, the logic cells include both combinatorial and registered connections with the programmable interconnect structure. Moreover, one of the sequential elements may selectively receive a dedicated input from the programmable interconnect structure. The output leads of the logic cell is connected to the programmable interconnect structure through a driver that includes a protection transistor. The gate of the protection transistor is coupled to a primary charge pump that is shared with multiple drivers as well as a secondary charge pump associated with the driver.