The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 30, 2002
Filed:
May. 04, 2000
Applicant:
Inventors:
Dinesh Saigal, San Jose, CA (US);
Shankarram Athreya, Sunnyvale, CA (US);
Kenny King-Tai Ngan, Fremont, CA (US);
Lisa L. Yang, San Jose, CA (US);
Assignee:
Applied Materials, Inc., Santa Clara, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/144 ;
U.S. Cl.
CPC ...
H01L 2/144 ;
Abstract
A method of forming solder bumps on a semiconductor wafer utilizing a low temperature biasable electrostatic chuck. In particular, the method comprises the steps of providing at least one bond pad on the semiconductor wafer, forming a barrier layer over the bond pad, and forming the solder bumps upon the at least one bond pad. By controlling the temperature and biasing of the electrostatic chuck, the barrier layer, such as nickel vanadium, exhibits a low tensile or compressive stress.