The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 30, 2002
Filed:
Aug. 17, 1999
Tung-Po Chen, Tai-Chung, TW;
Abstract
A method for manufacturing an embedded DRAM with self-aligned borderless contacts is provided. The method comprises providing a substrate having a first device region and a second device region. The first device region comprises a first transistor and the second device region has a second transistor. A silicide block layer is formed over the second device region. An etching stop layer covers all device regions. A mask layer covers the first device region. Then the etching stop layer not covered by the mask layer is removed. A first dielectric material layer is formed on all the device regions and therein a first contact window is on the second device region. A second dielectric material layer is next formed and therein a second contact window is on the second device region. A third dielectric material layer is formed and therein at least a third contact window is coupled to the first transistor of the first device region. A borderless contact is consisted of the contact window coupled to the substrate and a metallic node on the contact window.