Architecture of discrete wavelet transformation

Abstract

A VLSI wavelet transform (WT) architecture suitable for use in a discrete wavelet transform (DWT) or a discrete wavelet packet transform (DWPT). The WT architecture has a multiplier; an accumulator; at least two address generators that has a first address generator and a second address generator; a control unit; a memory of result that stores computation results; and a memory of table, which pre-stores all possible weights, each of which weights is a product of some specified filter coefficients for performing a DWT/DWPT with parameters of decomposition level, length of data segment, and filter length. The first address generator and the control unit receive data input, the control unit exports control signals to multiplier, accumulator, second address generator, and memory of table. The memory of the table also receives outputs from the first address generator and the second address generator to select the desired weights of the filter coefficients, which are sent to the multiplier to obtain a product with the data input. The product is sent to the accumulator to add into a corresponding sum, and the memory of result receives the corresponding sum and an address output of the second address generator to address the received corresponding sum, in which when all of the data input in the DWT/DWPT are completely inputted, each the corresponding sum is an end result of the DWT/DWPT.