The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 09, 2002

Filed:

Sep. 03, 1998
Applicant:
Inventors:

Chung-Shih Tsai, Chiayi Hsien, TW;

Der-Tgyr Fan, Taipei Hsien, TW;

Chou-Shin Jou, Hsin-Chu, TW;

Tings Wang, Hsin-Chu Hsien, TW;

Assignee:

Mosel Inc., Hsin-Chu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H07L 2/128 ;
U.S. Cl.
CPC ...
H07L 2/128 ;
Abstract

The present invention provides a method for controlling dopant density of a plug-shaped doped polysilicon layer formed within a plug-shaped recess to prevent the dopant contained in the plug-shaped doped polysilicon layer from diffusing into a conductive layer under the plug-shaped recess through a bottom side of the plug-shaped recess, the plug-shaped recess being formed within a dielectric layer which is positioned above the conductive layer, the method comprising: (1) forming an undoped silicon layer on the surface of the plug-shaped recess; (2) forming a doped polysilicon layer on top of the undoped silicon layer to fill the plug-shaped recess; and (3) performing a thermal treatment to the semiconductor wafer so as to make the doped poly-silicon layer interact with the undoped silicon layer inside the plug-shaped recess which forms a completely doped polysilicon layer within the plug-shaped recess.


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