Method and apparatus for scan of synchronized dynamic logic using embedded scan gates

Abstract

A method and apparatus for random-access scan of a network of dynamic logic or N-nary logic, wherein the network includes sequentially clocked precharge logic gates and one or more scan gates is disclosed. Each clocked precharge logic gate and each scan gate further comprise a logic tree having one or more evaluate nodes, a precharge circuit, an evaluate circuit, and one or more output buffers. Each scan gate further comprises a scan circuit that accepts scan control signals and couples to one or more scan registers in a RAM-like architecture. A scan control circuit generates scan control signals and scan timing signals which operate to capture the state of the output buffers of the scan gate and provide that state to one or more scan registers. Scan control signals and scan timing signals also operate to force the output buffers of the scan gate to a preselected level, which then propagates through the network to create an output state on the next scan gate in the network, which can then be read and compared to an expected output state given the output state of the previous scan gate.