The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 02, 2002

Filed:

Jun. 21, 1999
Applicant:
Inventors:

Jing-Reng Huang, Hsin-Chu, TW;

Chih-Tsun Huang, Hsin-Chu, TW;

Chi-Feng Wu, Hsin-Chu, TW;

Cheng-Wen Wu, Hsin-Chu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 3/128 ;
U.S. Cl.
CPC ...
G01R 3/128 ;
Abstract

In the present invention a built in self test (BIST) for an embedded memory is described. The BIST can be used at higher levels of assembly and for commodity memories to perform functional and AC memory tests. A BIST controller comprising a finite state machine is used to step through a test sequence and control a sequence controller. The sequence controller provides data and timing sequences to the embedded memory to provide page mode and non-page mode tests along with a refresh test. The BIST logic is scan tested prior to performing the built in self test and accommodations for normal memory refresh is made throughout the testing. The BIST also accommodates a burn-in test where unique burn-in test sequences can be applied.


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