The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 02, 2002
Filed:
Jun. 16, 2000
Sufi Zafar, Austin, TX (US);
Ramachandran Muralidhar, Austin, TX (US);
Bich-Yen Nguyen, Austin, TX (US);
Sucharita Madhukar, Austin, TX (US);
Daniel T. Pham, Austin, TX (US);
Michael A. Sadd, Austin, TX (US);
Chitra K. Subramanian, Austin, TX (US);
Motorola, Inc., Schaumburg, IL (US);
Abstract
A semiconductor device that includes a floating gate made up of a plurality of pre-formed isolated storage elements ( ) and a method for making such a device is presented. The device is formed by first providing a semiconductor layer ( ) upon which a first gate insulator ( ) is formed. A plurality of pre-fabricated isolated storage elements ( ) is then deposited on the first gate insulator ( ). This deposition step may be accomplished by immersion in a colloidal solution ( ) that includes a solvent and pre-fabricated isolated storage elements ( ). Once deposited, the solvent of the solution ( ) can be removed, leaving the pre-fabricated isolated storage elements ( ) deposited on the first gate insulator ( ). After depositing the pre-fabricated isolated storage elements ( ), a second gate insulator ( ) is formed over the pre-fabricated isolated storage elements ( ). A gate electrode ( ) is then formed over the second gate insulator ( ), and portions the first and second gate insulators and the plurality of pre-fabricated isolated storage elements that do not underlie the gate electrode are selectively removed. A source region ( ) and a drain region ( ) are then formed in the semiconductor layer ( ) such that a channel region is formed between underlying the gate electrode ( ).