The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 25, 2002

Filed:

Nov. 14, 2001
Applicant:
Inventors:

Hiroaki Tanizaki, Hyogo, JP;

Shigeki Tomishima, Hyogo, JP;

Mitsutaka Niiro, Hyogo, JP;

Masanao Maruta, Hyogo, JP;

Hiroshi Kato, Hyogo, JP;

Masatoshi Ishikawa, Hyogo, JP;

Takaharu Tsuji, Hyogo, JP;

Hideto Hidaka, Hyogo, JP;

Tsukasa Ooishi, Hyogo, JP;

Assignee:

Other;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/14 ;
U.S. Cl.
CPC ...
G11C 5/14 ;
Abstract

A first power supply voltage is supplied to a power supply node of a sense amplifier. A bit line driver outputs a column select signal composed of a second power supply voltage to the gate terminals of N channel MOS transistors of a GIO line gate circuit. When input/output data is [ , a third power supply voltage lower than the first power supply voltage is supplied onto a global data line. In this case, with a threshold voltage of N channel MOS transistors used, a relation is established: second power supply voltage≦third power supply voltage+threshold voltage. As a result, a leakage current can be reduced in a semiconductor memory device driven by plural power supply voltages with respective different voltage levels.


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