The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 25, 2002
Filed:
Oct. 15, 1998
Frederick N. Hause, Austin, TX (US);
Mark I. Gardner, Cedar Creek, TX (US);
Charles E. May, Austin, TX (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
A transistor and a method for making a transistor are described. A metal layer is formed upon a semiconductor substrate, and a masking layer is formed upon the metal layer. The masking layer is patterned to form an opening therein, and portions of the metal layer not covered by the masking layer are removed. A gate dielectric layer is formed within the opening upon the semiconductor substrate; in an embodiment, spacers are also formed upon opposed sidewall surfaces of the masking layer. A conductive material is then deposited upon the dielectric material to form a gate conductor. The masking material is then removed, source and drain and lightly doped drain impurity areas are formed in the semiconductor substrate, and the metal layer is annealed to form a silicide in close proximity to the channel region. By depositing the metal layer prior to forming the gate conductor, the process described herein allows formation of a metal silicide adjacent or in close proximity to the channel region of the transistor. The process also allows formation of a metal gate conductor self-aligned with lightly doped drain or source-drain impurity areas.