The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 18, 2002
Filed:
Jun. 30, 2000
Applicant:
Inventors:
Keng L. Wong, Portland, OR (US);
Hung-Piao Ma, Portland, OR (US);
Songmin Kim, Beaverton, OR (US);
Chi-Yeu Chao, Portland, OR (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/22 ;
U.S. Cl.
CPC ...
H03K 5/22 ;
Abstract
A dual mode clock input buffer is disclosed. The input buffer includes a first portion for handling a single ended high voltage clock signal and a second portion for handling a differential low voltage clock signal.
Wong, Keng. (2002). Self-configurable clock input buffer compatible with high-voltage single-ended and low-voltage differential clock signals (U.S. Patent No. 6407591). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6407591
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile