The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 18, 2002

Filed:

Apr. 06, 2000
Applicant:
Inventors:

Steven J. Brunelle, Boise, ID (US);

Phoung A. Nguyen, Nampa, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 3/102 ;
U.S. Cl.
CPC ...
G01R 3/102 ;
Abstract

A test module for simultaneously testing a plurality of IC packages in a simulated multi-chip module environment. The test module includes a module board adapted to receive the IC packages and a plurality of module adapters configured to secure the IC packages to the module board. The module adapters secure the IC packages to the module board and establish electrical contact between the IC package leads and a plurality of contact pads disposed on the module board, with no permanent bonding agent. Reliable electrical connections are established between the IC package leads and the contact pads by a plurality of protruding pins extending from each module adapter, which bias the IC package leads towards the contact pads. A plurality of IC packages assembled into the test module may be subjected to module level testing. During any stage of module level testing, any of the IC packages may be easily removed from the test module without the attendant damage resulting from severing of permanent electrical bonds ordinarily formed between the IC package leads and a conventional multi-chip module substrate. If the IC packages assembled into the test module exhibit specified operational characteristics during module level testing, the IC packages may be removed from the test module without damage and permanently assembled into a multi-chip module.


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