The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 18, 2002

Filed:

Nov. 04, 1997
Applicant:
Inventor:

Walter H. Schroen, Dallas, TX (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/300 ; H01L 2/302 ; H01L 4/900 ;
U.S. Cl.
CPC ...
H01L 2/300 ; H01L 2/302 ; H01L 4/900 ;
Abstract

An integrated circuit package ( ) may include an integrated circuit chip ( ) having an integrated circuit ( ). A lead frame ( ) may be opposite the integrated circuit chip ( ). The lead frame ( ) may include at least one lead ( ) electrically coupled to the integrated circuit ( ) by a connector ( ). The lead ( ) may be within a periphery ( ) of the integrated circuit chip ( ). An encapsulant ( ) may cover the integrated circuit ( ), the connector ( ) and a portion of the lead frame ( ). A remaining portion of the lead frame ( ) may be exposed from the encapsulant ( ).


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Schroen, Walter. (2002). Wafer level packaging (U.S. Patent No. 6407333). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6407333

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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