Method for backside failure analysis requiring simple bias conditions

Abstract

A method for conducting backside failure analysis on a wafer that only requires simple bias conditions to be fed into defective IC dies and a wafer test specimen which enables such test are disclosed. In the method, a wafer can be first provided that contains at least one defective IC die in an active (or front) surface, at least two conductive metal strips formed of a metal foil are then adhesively bonded to the active surface of the wafer juxtaposed to the at least one defective IC die. At least two lead wires are then bonded by a wire bonding technique between the at least two conductive metal strips and at least two bond pads on the defective IC die for establishing electrical communication therein between. A bias voltage such as a VCC signal or a clock signal can then be fed to the defective IC die through the at least two conductive metal strips, while the defect being observed from the backside of the wafer with an optical detector. The present invention novel method and the wafer test specimen enable the method to be executed at a relatively low cost and a shortened analysis time since a complete wafer can be tested without first been severed and packaged into IC chips as normally required in conventional test methods. Furthermore, the present invention novel test method can be executed on selected defective IC dies on a wafer without disturbing, or damaging other good dies.