The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 11, 2002
Filed:
Jan. 11, 2000
Peivand Fallah-Tehrani, Thousand Oaks, CA (US);
Shang-Woo Chyou, Westlake Village, CA (US);
Synopsys, Inc., Mountain View, CA (US);
Abstract
A method for static timing analysis of deep sub-micron devices in presence of crosstalk. The present invention provides an efficient platform for fast and accurate static timing verification of large scale transistor and cell level netlists, with coupled interconnects and high switching speeds. The present invention also provides a novel approach to solve the coupled noise problem in static timing verification. The present invention also provides for a method of determining worst case aggressor switching time for a cross-coupled interconnect stage. After the worst case aggressor switching time is determined, the netlist is then resimulated using the worst case aggressor switching time to determine more accuate stage delay and slew of the interconnect stage. The output waveform is recorded and utilized as the input of subsequent stages.