The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 11, 2002

Filed:

Jul. 27, 1999
Applicant:
Inventors:

Jitske Trevor, Sunnyvale, CA (US);

Shashank Deshmukh, Sunnyvale, CA (US);

Jeff Chinn, Foster City, CA (US);

Assignee:

Applied Materials, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
C23F 7/00 ;
U.S. Cl.
CPC ...
C23F 7/00 ;
Abstract

In accordance with the present invention, during a polysilicon etch back, a controlled amount of oxygen (O ) is added to the plasma generation feed gases, to reduce pitting of the etched back polysilicon surface. The plasma etchant is generated from a plasma source gas comprising: (i) at least one fluorine-containing gas, and (ii) oxygen. The invention may be practiced in any of a number of apparatus adapted to expose polysilicon to a plasma etchant. One preferred apparatus is a decoupled plasma source (DPS™, Applied Materials, Santa Clara, Calif.) etching system. Another preferred apparatus is a magnetically enhanced plasma (MXP™, Applied Materials, Santa Clara, Calif.) etching system. Preferably, the invention is practiced in an apparatus having a memory that stores instructions for carrying out the process of the invention, a processor adapted to communicate with the memory and to execute the instructions stored by the memory, an etch chamber adapted to expose the substrate to the etchant in accordance with instructions from the processor, and a port adapted to pass communications between the processor and the etch chamber.


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