The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 11, 2002
Filed:
Oct. 05, 1998
Janos Legrady, Putnam Valley, NY (US);
Zierick Manufacturing Corp., Mount Kisco, NY (US);
Abstract
A capillary action enhanced surface mount pin header includes a first flat substrate provided with a predetermined array of plated-through holes having substantially parallel and each having an internal surface defining a first substantially uniform cross section. Pins are provided each of which defines a longitudinal axis and having one end extending through an associated plated-through hole and another end extending to one side of said first substrate. Each pin has an external surface on at least a portion thereof which is received within an associated plated-through hole which defines a second substantially uniform cross section. In the disclosed embodiment, the pins have square or hexagonal cross sections while the plated-through holes have circular cross sections. The first and second cross sections are dissimilar and configured to provide spaced lines of contact and elongate channels substantially parallel to the axes between the internal and external surfaces and adjacent lines of contact, dimensioned to promote capillary action for molten solder at a channel opening on one side of the first substrate to cause the solder to be drawn through the channels towards the opposite side of the first substrate. A second substantially flat substrate is provided for positioning the solder at points substantially aligned with points on the predetermined array and proximate to at least one channel in at least one plated-through hole prior to melting of the solder.