The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 28, 2002
Filed:
Apr. 20, 2000
Felice Balarin, Berkeley, CA (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
A general methodology for worst-case analysis of systems with discrete observable signals is disclosed. According to one embodiment, a signature &sgr; is chosen and a &sgr;-abstraction F is created, based on the system and the particular property to be analyzed. This procedure requires a user to facilitate the creation of an appropriate signature and &sgr;-abstraction. Next, for a given length of time T, a signature s is determined. From the signature s the worst-case boundary conditions are determined. The methodology may also be applied to timing analysis of embedded systems implemented on a single processor. The procedure calculates a time T which is an upper bound on the time a processor can be busy (i.e. busy period). Thus, for the busy-period analysis, the time T is no longer fixed. As in the first embodiment, a signature &sgr; is selected and a &sgr;-abstraction F is created. A workload function R is chosen, and a signature s and time T are calculated. The calculated time T is an upper bound on the length of a busy period for the given system.