Semiconductor device comprising a test structure

Abstract

A semiconductor memory device comprising a test structure is disclosed. The semiconductor device includes a plurality of memory cells, word lines, bit lines, and test pads; the word lines including a first set and a second set of word lines, connected to a first and second word line test pad, respectively; the bit lines including a first set and a second set of bit lines, connected to a first and second bit line test pad, respectively. The first set of word lines and the first set of bit lines access a first set of memory cells, the first set of word lines and the second set of bit lines access a second set of memory cells, the second set of word lines and the first set of bit lines access a third set of memory cells, and the second set of word lines and the second set of bit lines access a fourth set of memory cells. By applying a predetermined set of test signals to the first and second word line test pads, and the first and second bit line test pads, the disturbance or interference among the first, second, third, and fourth set of memory cells can be measured.