The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 28, 2002

Filed:

Dec. 30, 1999
Applicant:
Inventors:

Akira Nagai, Hitachi, JP;

Takumi Ueno, Mito, JP;

Haruo Akahoshi, Hitachi, JP;

Syuji Eguchi, Tokai-mura, JP;

Masahiko Ogino, Hitachi, JP;

Toshiya Satoh, Kanasagou-machi, JP;

Asao Nishimura, Kokubunji, JP;

Ichiro Anjoh, Koganei, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/348 ; H01L 2/352 ; H01L 2/940 ; H01L 2/144 ;
U.S. Cl.
CPC ...
H01L 2/348 ; H01L 2/352 ; H01L 2/940 ; H01L 2/144 ;
Abstract

A semiconductor device includes a semiconductor element arranged to form integrated circuitry, a plurality of electrode pads formed on the side of the integrated circuitry formation surface of the in semiconductor element, bump electrodes for external connection electrically connected to the electrode pads through a conductive layer, and a stress relaxation layer formed between the integrated circuitry formation surface and electrode pads on one hand and the bump electrodes and conductive layer on the other hand, the stress relaxation layer being adhered thereto, wherein more than one third of the stress relaxation layer from a surface thereof is cut away for removal and wherein the stress relaxation layer is subdivided into a plurality of regions.


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