Design layout for a dense memory cell structure

Abstract

A design layout for a memory cell structure is provided that achieves maximized channel length on the active areas, while not constricting the contact area of the capacitor contacts is provided. Specifically, the layout design provides a semiconductor memory structure that includes wordlines, bitlines, and sub-8F memory cells in a semiconductor substrate, said memory cells comprising a transfer gate transistor having a source region and a drain region formed in said substrate and a gate electrode, a memory cell stacked storage capacitor, a wordline conductor portion contacting said gate electrode, said wordline gate conductor portion forming part of one of said wordlines, a bitline contact to said source region, said bitline contact connecting said source region to one of said bitlines, and a capacitor contact between said capacitor and said drain region, wherein for at least one of said cells, said bitline contact and said capacitor contact are positioned at a distance from each other greater than from said bitline contact to a closest contact of another of said cells and greater than from said capacitor contact to a closest contact of another of said cells.