The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 28, 2002

Filed:

May. 31, 2001
Applicant:
Inventors:

Jao-Chin Cheng, Hsinchu, TW;

Chang-Chin Hsieh, Taipei, TW;

Chih-Peng Fan, Taipei Hsien, TW;

Chin-Chung Chang, Taoyuan, TW;

Assignee:

World Wiser Electrics Inc., Taoyuan Hsien, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/144 ;
U.S. Cl.
CPC ...
H01L 2/144 ;
Abstract

A method of forming a micro-via, for fabrication and design of a layout of a circuit board. A patterned conductive wiring layer is formed on the substrate. A copper layer is plated onto the substrate and the conductive wiring layer. A photoresist layer is formed on the copper layer. A part of the photoresist layer is removed to expose a part of the copper layer. Using the copper layer as a seed layer, a conductive pillar is formed on the exposed part of the copper layer. The photoresist layer is removed. The exposed plated copper layer is removed. An insulation layer is formed on surfaces of the substrate and the conductive pillar. A part of the insulation layer is removed to expose the conductive pillar. A patterned conductive wiring layer is formed on the conductive pillar.


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