Dual port programmable logic device variable depth and width memory array

Abstract

A dual-port programmable logic device memory array is provided. Selectable-size data words may be written to and read from the array concurrently. Data is written into the array using write column decoder and data selection logic. The size of the data words handled by the write column decoder and data selection logic is controlled by mode select signals. Data is read from the array using read column decoder and data selection logic. The size of the data words handled by the read column decoder and data selection logic is also controlled by mode select signals. The write column decoder and data selection logic may be used to write data into the memory array at one selected location at the same time that the read column decoder and data selection logic is used to read data from the array at another selected location. A write row address decoder and a read row address decoder are used to independently address individual rows of memory cells in the memory array during writing and reading, respectively.