Triggered integrated circuit tester

Abstract

A triggered integrated circuit (IC) tester in accordance with the invention organizes a test of an IC into a succession of test cycles. A vector generated prior to the start of each test cycle references the test activities to be carried out during the test cycle. The tester generates a set of N periodic timing signals, T through T(N−1), each having a period equal to the duration of one test cycle with the timing signals being distributed in phase so that their edges evenly divide each test cycle into N intervals. Each test cycle nominally starts on an edge of the T signal, and each vector referencing a test event also indicates a nominal time delay following the start of the test cycle at which the event is to occur by referencing one of the timing signals T through T(N−1). However whenever the tester receives an input trigger signal edge, it determines an offset between the most recent T signal edge and the occurrence of the trigger signal edge. During subsequent test cycles, the tester delays the start of test cycles and occurrence of test events by the amount of the trigger signal edge offset. In doing so, the tester makes the delay of each subsequent test event with respect to the trigger signal edge a predictable function of the vector sequence.