Forming complementary metal-oxide semiconductor with gradient doped source/drain

Abstract

The present invention provides a method for forming a transistor with a gradient doped source/drain. The method comprises the following steps. First, two first N-wells are formed in a substrate and the first N-wells are separated in both sides of the substrate. The, two second N-wells are formed in the substrate and the second N-wells overlie the first N-wells. An implanting concentration of first N-wells is smaller than an implanting concentration of second N-wells. Next, a field oxide region is formed in the substrate between the first N-wells and the field oxide region overlies on a portion of second N-wells. Thereafter, portion of the field oxide region and the substrate are removed to form a trench n the substrate, wherein the remaining field oxide region overlies on the second N-wells. Next, a gate oxide layer is formed on a bottom surface and sidewall of the trench. Then, a polysilicon gate is formed on the substrate. The trenches filled with the polysilicon gate and the polysilicon gate overlies a portion of the remained field oxide region. Last, a N -type source/drain is formed in the substrate and the N -type source/drain is adjacent to the remaining field oxide region and overlies the second N-wells.