The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 14, 2002
Filed:
Mar. 25, 1999
Visweswara Rao Kodali, Austin, TX (US);
Johnny James LeBlanc, Austin, TX (US);
Kevin William McCauley, Greene, NY (US);
Salim Ahmed Shah, Austin, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method and implementing system is provided in which input signal specifications, element internal delays and output loads, for each element in a circuit design, are utilized in an iterative processing engine to objectively determine and provide a timing rule database for a circuit being designed. A schematic database netlist is run through a test model converter program to provide a test model database at a gate level for the test model design circuit. These data are processed by a designer through a workstation GUI and the result is applied to an I/O design testing function. The results of the I/O design testing function include a listing of patterns of input combinations which are needed to get listed outputs. The GUI prepares a sequence of stimuli to test the circuit with a timing simulator. Based on the output response of the timing simulator, delay relationships under various input and output load conditions are compiled.