The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 14, 2002
Filed:
Sep. 06, 2000
Pin-Chin C. Wang, Menlo Park, CA (US);
Christy M. Woo, Cupertino, CA (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
An interconnect opening of an integrated circuit is filled with a conductive fill, such as copper, with the interconnect opening being within an insulating layer on a semiconductor wafer. A seed layer of a first alloy is deposited conformally onto sidewalls and a bottom wall of the interconnect opening. The first alloy is comprised of a first metal dopant in a bulk conductive material. The first metal dopant has a relatively high solid solubility in the bulk conductive material, and the first metal dopant has a concentration in the bulk conductive material of the seed layer that is lower than the solid solubility of the first metal dopant in the bulk conductive material. At least a portion of the conductive fill grown from the seed layer is comprised of a second alloy with a second metal dopant having a relatively low solid solubility in the bulk conductive material, and the second metal dopant has a concentration in the conductive fill that is higher than the solid solubility of the second metal dopant in the bulk conductive material. A thermal anneal is performed to form an additional encapsulating material that covers a top surface of the conductive fill, and the additional encapsulating material is formed from the second metal dopant diffusing out of the conductive fill during the thermal anneal. A layer of bulk passivation material is formed over the additional encapsulating material and the insulating layer. Use of the first alloy of the seed layer prevents agglomeration of the bulk conductive material of the seed layer at the sidewalls of the interconnect opening. The additional encapsulating material prevents drift of material from the conductive fill along the bottom surface of the layer of bulk passivation material and into the surrounding insulating layer.