Method of making vertical field effect transistor having channel length determined by the thickness of a layer of dummy material

Abstract

For fabricating a vertical field effect transistor on a semiconductor substrate, a bottom layer of doped insulating material is deposited on the semiconductor substrate. A layer of dummy material is deposited on the bottom layer of doped insulating material. A top layer of doped insulating material is deposited on the layer of dummy material. An opening is etched through the top layer of doped insulating material, the layer of dummy material, and the bottom layer of doped insulating material. A semiconductor fill is contained within the opening. The semiconductor fill has at least one sidewall with a top portion of the sidewall abutting the top layer of doped insulating material, a middle portion of the sidewall abutting the layer of dummy material, and a bottom portion of the sidewall abutting the bottom layer of doped insulating material. The layer of dummy material is etched away such that the middle portion of the sidewall of the semiconductor fill is exposed. A gate electrode opening disposed between the top and bottom layers of doped insulating material is formed when the layer of dummy material is etched away. A gate dielectric of the vertical field effect transistor is formed on the exposed middle portion of the sidewall of the semiconductor fill. The electrode opening between the top and bottom layers of doped insulating material is filled with electrode material to form a gate electrode on the dielectric. Dopant diffuses from the bottom and top layers of doped insulating material into the bottom and top portions of the semiconductor fill to form first and second drain or source extension junctions respectively.