The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 07, 2002
Filed:
Mar. 30, 1999
Applicant:
Inventors:
Ping Chen, San Jose, CA (US);
Wern-Yan Koe, San Jose, CA (US);
Assignee:
NEC Electronics, Inc., Santa Clara, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 3/128 ;
U.S. Cl.
CPC ...
G01R 3/128 ;
Abstract
A method and circuit for allowing direct access logic testing in integrated circuits. In one embodiment, an interface between integrated circuit core logic and integrated circuit user-defined logic is exposed, and the integrated circuit core logic and the integrated circuit user-defined logic is tested via the exposed interface. In another embodiment, an integrated circuit has logic selection circuitry connected with core logic and user-defined logic. The logic selection circuitry is used to selectively test the core logic and user-defined logic.